1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device achieving effective use of a chip area by preventing current paths from concentrating heavily in a structure in which first and second electrodes respectively connected to input and output portions are provided on one of main surfaces.
2. Description of the Related Art
A semiconductor device of a discrete semiconductor (a semiconductor chip) is often provided with electrodes respectively disposed on both main surfaces (a front surface and a back surface) of a chip to be respectively connected to input and output portions. There is also known a surface-mountable type of semiconductor provided with two electrodes disposed on one main surface of a chip.
By referring to FIG. 4, the conventional surface mountable type of semiconductor device will be described by using a MOSFET as an example. FIG. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the b-b line of FIG. 4A.
An n− type semiconductor layer 111 is provided on an n+ type semiconductor substrate 110, and a p type impurity layer 112 is provided in the n− type semiconductor layer 111. Trenches 115 are formed to reach the n− type semiconductor layer 111 from a surface of the p type impurity layer 112. The inner walls of the trenches 115 are covered with a gate insulating film 116. Then, gate electrodes 117 are formed by burial in the trenches 115. Thereby, a number of MOFFET cells are provided. On a surface of the p type impurity layer 112, which is adjacent to the trench 115, n+ type source regions 114 are formed. The trenches 115 are covered with interlayer insulating films 118.
A source electrode 120 is provided to be connected to each of the source regions 114 of each cell. A gate pad electrode 121a is connected to the gate electrode 117 by a metal gate wiring 121 and a polysilicon gate wiring 125. A drain electrode 122 is provided on an n+ type region 123 in one end side region of a chip. In addition, a conductive regions 119 is provided to reach the n+ type semiconductor substrate 110 from the surface of the n+ type region 123 though the n− type semiconductor layer 111. The conductive regions 119 is in contact with the drain electrode 122.
A soldering bump 126 to be an external connection terminal is provided on each of the gate pad electrode 121a, the source electrode 120, and the drain electrode 122 (see, for example, Japanese Patent Application Publication No. 2002-353452).
In addition, FIG. 5 is a view showing a chip end portion of a general MOSFET. FIG. 5 shows a configuration provided with the source electrode 120 on one of main surfaces of a substrate and also provided with the drain electrode 122 on the other main surface thereof. The other configurations are similar to those of FIG. 4. Accordingly, the same reference numerals as those used in FIG. 4 are given to denote components similar to those of FIG. 4, and the description thereof will be omitted.
As shown in FIG. 5, in order to secure a predetermined breakdown voltage in a MOSFET, a so-called guard ring 150 is provided in an end portion of the p type impurity layer (a channel layer) 112 in which cells are disposed. In the guard ring 150, a p type impurity is diffused with high concentration. In addition, in order to prevent a substrate surface from being reversed, and to terminate expansion of a depletion layer, high concentration impurity region (an annular region) 151 is disposed in the outermost circumference of the substrate. A metal layer (shield metal) 152, which is in contact with the annular region and is not applied with any potential, is disposed on the annular region 151. The shield metal 152 is a metal layer disposed in the outermost circumference of the chip (see, for example, Japanese Patent Application Publication No. 2005-101334, on page 19, FIG. 8).
In the structure of FIG. 4, main current paths between the source electrode 120 and the drain electrode 122 are formed, as shown by arrows (in FIG. 4A), from the lower side of the source electrode 120 in which the cells are disposed, towards the conductive regions 119 and the drain electrode 122 which are disposed on one side of the chip. That is, current components gather in one region where the conductive regions 119 are collectively disposed. Accordingly, there has been a problem that on-resistance is high.
There has also been a problem that a current is biased because a difference of resistance components in a lateral direction is caused between the cells closer to the drain electrode and the cells far therefrom.
In addition, the conductive regions 119 to draw a current to the drain electrode 122, which is provided on the same main surface as that of the source electrode 120, is formed by filling the trench provided in the substrate with a conductive material, such as polysilicon or a metal layer.
In addition, as shown in FIG. 5, in the discrete device such as a MOSFET, the high concentration impurity region (the annular region) 151 in which an impurity is diffused with high concentration is provided in the end portion of the substrate, and prevents the depletion layer from reaching the end portion of the substrate. For example, there is a case where the depletion layer expanded from the guard ring reaches the end portion of the substrate when VDSS (reverse bias between a drain and a source when a gate and the source are shorted out) is applied. As a result, there is a problem that a leak current is generated.
The annular region 151 is provided in the chip end portion so as to prevent the depletion layer from reaching the chip end portion. In addition, since the annular region 151 only has to prevent the depletion layer from reaching to the chip end portion, the annular region 151 is provided in a region whose depth from the surface is relatively shallow. In addition, the annular region 151 is provided at a sufficiently-long distance from the end portion of the device region (for example, the guard ring 150) (so as not to deteriorate a breakdown voltage) in consideration of the expansion of the depletion layer. Moreover, the depletion layer from reaching the chip end portion is more effectively prevented, if widths of the annular region 151 and the metal layer (the shield metal) 152 being in contact with the annular region 151 are set to be large.
In this manner, in the case of a so-call up-drain structure in which the drain electrode 122 and the source electrode 120 are provided on the one main surface side of the chip, the conductive regions 119 for drawing a current to the drain, the drain electrode 122 and even the annular region 151 need to be disposed on the one main surface side. This causes a problem that a region in the chip end portion requires such a large area as to increase the chip size.
In contrast, if the chip size is kept from increasing, then the device region is narrowed. Accordingly, for example, a MOSFET has a problem of an increase of on-resistance.